1. Field of the Invention
The present invention relates to a semiconductor device and more particularly, to a semiconductor device with a bipolar transistor operable in the microwave region, in which the parasitic capacitance of the transistor is reduced.
2. Description of the Prior Art
In general, the power gain .vertline.S.sub.21e .vertline..sup.2 of a bipolar transistor operated in a High-Frequency (HF) range whose frequency f is several hundreds MHz or greater, which is termed a microwave bipolar transistor, is expressed by the following equation (1). ##EQU1##
In the equation (1), Z.sub.0 is the characteristic impedance. f.sub.T is the cutoff or transition frequency, .gamma..sub.b is the base resistance, .gamma..sub.e is the emitter resistance, and C.sub.CB is the collector-base capacitance.
It is seen from the equation (1) that the power gain .vertline.S.sub.21e .vertline..sup.2 is strongly dependent upon the collector-base capacitance C.sub.CB. Thus, to increase the power gain .vertline.S.sub.21e .vertline..sup.2 by means of reducing the collector-base capacitance C.sub.CB, some improved transistor structures have been developed and disclosed.
FIG. 1 shows a first example of the conventional improved transistor structures, which is disclosed in the Japanese Non-Examined Patent Publication No. 2-246223 published in 1990.
As shown in FIG. 1, a field oxide 133 is selectively formed on a semiconductor substrate 132 to define a device region in the surface area of the substrate 132. An intrinsic base region 134 is formed in the device region of the substrate 132. An emitter region 136 is formed in the device region of the substrate 132 to be surrounded by the intrinsic base region 134.
An emitter contact layer 146 is formed on a silicon dioxide (SiO.sub.2) layer 140 to be contacted with and electrically connected to the emitter region 136. An emitter electrode 145 is formed on the emitter contact layer 146 to be electrically connected to the emitter region 136 through the emitter contact layer 146.
An extrinsic base region 135 is formed in the device region of the substrate 132 to be contacted with the intrinsic base region 134. As seen from FIG. 1, the extrinsic base region 135 is located at only one side (i.e., the right-hand side in FIG. 1) of the intrinsic base region 134. The extrinsic base region 135 is electrically connected to a base electrode 144 through a base connection layer 139 formed on the field oxide 133.
At an opposite side of the intrinsic base region 134 to the extrinsic base region 135, a high-resistivity layer 141 is formed on the field oxide 133 to be contacted with the device region of the substrate 136.
A SiO.sub.2 layer 140 is formed on the field oxide 133 to be contacted with the device region of the substrate 132. The emitter contact layer 146 and the base electrode 144 are formed on the SiO.sub.2 layer 140.
As described above, the conventional bipolar transistor shown in FIG. 1 has a so-called "single base structure" and therefore, the capacitance of the base-collector junction is decreased compared with the case where the extrinsic base region 135 is provided at both sides of the intrinsic base region 134.
However, with the conventional bipolar transistor shown in FIG. 1, because the base connection layer 139 is formed to extend over the device region of the substrate 132 serving as the collector region through the field oxide 153, a parasitic capacitance will occur between the base connection layer 139 and the substrate 132. This parasitic capacitance causes a problem that the power gain .vertline.S.sub.21e .vertline..sup.2 in a HF region is lowered.
FIG. 2 shows a second example of the conventional improved transistor structures, which is disclosed in the Japanese Non-Examined Patent Publication No. 6-342801 published in 1994.
As shown in FIG. 2, a field oxide 153 is selectively formed on a silicon substrate 151 to define a device region in the surface area of the substrate 151. A channel stop region 161 is formed below the field oxide 143. The device region of the substrate 151 serves as a collector region 152a and a collector connection region 152b.
A base region 154 and an emitter region 156 are formed in the device region of the substrate 151. The base region 154 is located on the collector region 152a and the emitter region 156 is surrounded by the base region 154.
The collector connection region 152b is electrically connected to a collector electrode 167 through a collector contact layer 168 made of polysilicon. The emitter region 156 is electrically connected to an emitter electrode 165 through an emitter contact layer 166 made of polysilicon. The base region 154 is electrically connected to a base electrode 164 through a base connection layer 159 made of polysilicon. The base connection layer 159 is formed on the thick field oxide 153,
As described above, with the conventional bipolar transistor shown In FIG. 2, the base region 154 is laterally contacted with and electrically connected to the base connection layer 159, extending over the thick field oxide 153 and therefore, the size of the base region 154 can be reduced. As a result, the capacitance of the collector-base junction in the device region is lowered.
However, because the base connection layer 159 is formed to extend over the collector region 152a and the connection region 152b, a parasitic capacitance will occur between the base connection layer 159 and the collector region 152a and the collector connection region 152b. This parasitic capacitance causes the same problem as above,
FIG. 3 shows a third example of the conventional improved transistor structures, which is disclosed in the Japanese Non-Examined Patent Publication No. 5-136434 published in 1993.
As shown in FIG. 3, abase region 174 is formed in an n-type epitaxial layer 172 that serves as a collector region. An emitter region 176 is formed in the epitaxial layer 172 to be surrounded by the base region 174. A collector connection region 177 is formed in the epitaxial layer 172.
A dielectric layer 173 is formed on the epitaxial layer 172. A collector electrode 181 is formed on the dielectric layer 173 to be contacted with and electrically connected to the collector connection region 177. A conductive layer 178 is formed on the dielectric layer 173 to be contacted with and electrically connected to the emitter region 176.
An interlayer dielectric layer 175 is formed on the conductive layer 178. An emitter electrode 182 is formed on the interlayer dielectric layer 175 to be contacted with and electrically connected to the conductive layer 178. Thus, the emitter electrode 182 is electrically connected to the emitter region 16 through the conductive layer 178.
A wiring layer 183 for a signal or signals is formed on the interlayer dielectric layer 175 to be overlapped with the underlying conductive layer 178.
As described above, with the conventional bipolar transistor shown in FIG. 3, the transistor is used as a collector-emitter (C-E) diode while the base region 174 is kept electrically open. The conductive layer 178, which is electrically connected to the emitter region 176, is located on the dielectric layer 173 and at the same time, the wiring layer 183 is located to be overlapped with the conductive layer 178 through the interlayer dielectric layer 175. Thus, a parasitic capacitance between the wiring layer 183 and the base region 174 is generated.
As clearly seen from the above explanation, the conventional bipolar transistor shown in FIG. 3 does not have the structure to decrease the collector-base capacitance C.sub.CB.
FIG. 4 shows a fourth example of the conventional improved transistor structures, which is disclosed in the Japanese Non-Examined Utility-Model Publication No. 2-98632 published in 1990.
As shown in FIG. 4, an n-type collector region 192 is formed on a silicon substrate 191. In the collector region 192, a p-type base region 194, a p.sup.- -type region 195, an n-type emitter region 196, and an n.sup.+ -type region 189 are formed. The base region 194 is contacted with the p.sup.- -type region 195.
A SiO.sub.2 layer 193 is formed on the collector region 192. A conductive layer 197 is formed on the SiO.sub.2 layer 193 to be contacted with and electrically connected to the n.sup.+ -type region 189. An interlayer dielectric layer 198 is formed to cover the conductive layer 197.
A base connection layer 199 is formed on the interlayer dielectric layer 198 to be contacted with and electrically connected to the base region 194. The base connection layer 199 is overlapped with the underlying conductive layer 197, resulting in an intentional parasitic capacitance between the base and collector regions 194 and 192.
With the conventional transistor structure shown in FIG. 4, because the conductive layer 197 is formed to extend over the collector region 192 through the SiO.sub.2 layer 193, a parasitic capacitance will occur between the conductive layer 197 and the collector region 192. This parasitic capacitance causes the same problem as above.